TVM Build

LowerSchedule:
  IRModule mod = ScheduleToModule(std::move(sch), args, name, binds);
  Array<transform::Pass> pass_list = CreatePassList(simple_mode, true);
  return LowerWithPassList(mod, pass_list);

ScheduleToModule:
  // InferBound 根据 split 的 factor 得到 itervar 及其循环的范围， 比如这里打印
  // 出 bounds 的信息:
  //
  // for (auto& p : bounds) {
  //     LOG_INFO << p.first << p.second;
  // }
  //
  // 打印出结果为:
  //
  // bound.cc:262: {<tir.IterVar>iter_var(x.outer, )}{<Range>range(min={<IntImm>0}, ext={<IntImm>2})}
  // bound.cc:262: {<tir.IterVar>iter_var(x, {<Range>range(min={<IntImm>0}, ext={<IntImm>10})})}{<Range>range(min={<IntImm>0}, ext={<IntImm>10})}
  // bound.cc:262: {<tir.IterVar>iter_var(x.inner, )}{<Range>range(min={<IntImm>0}, ext={<IntImm>5})}
  Map<tir::IterVar, Range> bounds = te::InferBound(sch);
  tir::Stmt stmt = te::ScheduleOps(sch, std::move(bounds), false);
    body = MakePipeline(s, dom_map, body, debug_keep_trivial_loop);
      Stmt producer = s->op->BuildProvide(s, dom_map,  debug_keep_trivial_loop);
        MakeComputeStmt(this, stage, dom_map, debug_ keep_trivial_loop);
          // 初始 body 中只有一条 stmt, 即 lambda(x) :A[x]+B[x] 通过 compute 生成 的 stmt
          // {<tir.ProducerStore>compute[{<tir.Var>x }] ={<tir.Add>({<tir.ProducerLoad>A[{<tir.Var>x}]} + {<tir.ProducerLoad>B[{<tir.Var>x}]})}
          for (size_t i = 0; i < self->body.size(); ++i) {
            provides.emplace_back(MakeProvide(self, stage->op.output(i)));
          }
          // MergeNest 最终根据 bounds (即 dom_map)  生成额外的循环语句，
          // MergeNest 返回的 stmt 为:
          //
          // {<tir.For>for ({<tir.Var>x.outer}, {<In tImm>0}, {<IntImm>2}) {
          //   {<tir.AttrStmt>  // attr [{<tir.IterV ar>iter_var(x.outer, )}] loop_scope = {<tir.Var>x.outer}
          //   {<tir.For>  for ({<tir.Var>x.inner},  {<IntImm>0}, {<IntImm>5}) {
          //     {<tir.AttrStmt>    // attr [{<tir.I terVar>iter_var(x.inner, )}] loop_scope = {<tir.Var>x.inner}
          //     {<tir.ProducerStore>    compute[{<t ir.Var>x}] ={<tir.Add>({<tir.ProducerLoad>A[{<tir.Var>x}]} + {<tir.ProducerLoad>B[{<tir.Var>x}]})}}}
          //   }}}}
          // }
          provide = MergeNest(n.main_nest, provide);

Array<tvm::transform::Pass> CreatePassList(bool disable_loop_partition, bool for_te_schedule) {
  transform::PassContext pass_ctx = transform::PassContext::Current();

  // Get any user-added passes
  Array<Array<ObjectRef>> add_lower_pass =
      pass_ctx->GetConfig<Array<Array<ObjectRef>>>("tir.add_lower_pass", Array<Array<ObjectRef>>())
          .value();

  Array<transform::Pass> user_lower_phase0 = Array<transform::Pass>();
  Array<transform::Pass> user_lower_phase1 = Array<transform::Pass>();
  Array<transform::Pass> user_lower_phase2 = Array<transform::Pass>();
  Array<transform::Pass> user_lower_phase3 = Array<transform::Pass>();

  // phase pasees is of the form
  // [[phase_number, pass], [phase_number, pass]... ]
  for (Array<ObjectRef> phase_pass : add_lower_pass) {
    const IntImmNode* phase_num = phase_pass[0].as<IntImmNode>();
    ICHECK(phase_num)
        << "Expected the first entry in the inner Array of tir.add_lower_pass to be an integer";
    int phase_num_val = phase_num->value;

    CHECK_GE(phase_num_val, 0);

    const tvm::transform::PassNode* pass_node = phase_pass[1].as<tvm::transform::PassNode>();
    tvm::transform::Pass pass = GetRef<tvm::transform::Pass>(pass_node);
    // Copy the pass into the correct phase
    if (phase_num_val == 0) {
      user_lower_phase0.push_back(pass);
    } else if (phase_num_val == 1) {
      user_lower_phase1.push_back(pass);
    } else if (phase_num_val == 2) {
      user_lower_phase2.push_back(pass);
    } else if (phase_num_val >= 3) {
      user_lower_phase3.push_back(pass);
    }
  }

  // Construct the pass list, inserting the user provided passes at the end of the phase

  // PHASE 0
  Array<tvm::transform::Pass> pass_list = user_lower_phase0;

  // PHASE 1
  if (for_te_schedule) {
    pass_list.push_back(tir::transform::InjectPrefetch());
    pass_list.push_back(tir::transform::StorageFlatten(64, instrument_bound_checkers));
  } else {
    pass_list.push_back(tir::transform::LowerInitBlock());
    pass_list.push_back(tir::transform::PlanAndUpdateBufferAllocationLocation());
    pass_list.push_back(tir::transform::ConvertBlocksToOpaque());
    pass_list.push_back(tir::transform::CompactBufferAllocation());
    pass_list.push_back(tir::transform::LowerMatchBuffer());
    pass_list.push_back(tir::transform::FlattenBuffer());
  }
  pass_list.push_back(tir::transform::BF16Legalize());
  pass_list.push_back(tir::transform::NarrowDataType(32));
  pass_list.push_back(tir::transform::Simplify());

  // Add user-defined phase-1 passes
  pass_list.insert(pass_list.end(), user_lower_phase1.begin(), user_lower_phase1.end());

  // PHASE 2
  if (!disable_loop_partition) {
    pass_list.push_back(tir::transform::LoopPartition());
  }

  pass_list.push_back(tir::transform::VectorizeLoop(!disable_vectorize));
  pass_list.push_back(tir::transform::InjectVirtualThread());
  pass_list.push_back(tir::transform::InjectDoubleBuffer());
  pass_list.push_back(tir::transform::StorageRewrite());
  pass_list.push_back(tir::transform::UnrollLoop());

  // Add user-defined phase-2 passes
  pass_list.insert(pass_list.end(), user_lower_phase2.begin(), user_lower_phase2.end());

  // PHASE 3
  pass_list.push_back(tir::transform::Simplify());
  pass_list.push_back(tir::transform::RemoveNoOp());
  pass_list.push_back(tir::transform::RewriteUnsafeSelect());
  pass_list.push_back(tir::transform::HoistIfThenElse());

  // Add user-defined phase-3 passes
  pass_list.insert(pass_list.end(), user_lower_phase3.begin(), user_lower_phase3.end());

  if (instrument_bound_checkers) {
    pass_list.push_back(tir::transform::InstrumentBoundCheckers());
  }
  return pass_list;
}